1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device and a method of manufacturing a semiconductor device.
2. Description of the Related Art
A known power semiconductor device has a vertical power semiconductor element and a horizontal semiconductor element for control and protection circuits of the vertical power semiconductor element provided on a single semiconductor substrate (a semiconductor chip) to enhance reliability and achieve reductions in the size and cost of the power semiconductor element (see, for example, Japanese Laid-Open Patent Publication Nos. 2002-359294 and 2000-91344). The structure of a traditional semiconductor device will be described taking an example of a power semiconductor device that has provided on a single semiconductor substrate, a vertical n-channel power metal oxide semiconductor field effect transistor (MOSFET) for an output stage and a horizontal complementary MOS (CMOS) for a control circuit. FIG. 13 is a cross-sectional diagram of the structure of the traditional semiconductor device.
The traditional semiconductor device depicted in FIG. 13 is an example of an in-vehicle, high-side power integrated circuit (IC) having a vertical MOSFET 110 of a trench gate structure as a vertical n-channel power MOSFET for the output stage. As depicted in FIG. 13, the traditional semiconductor device includes an output stage portion, a circuit portion, and a protective element portion that protects the output stage portion and the circuit portion from surges, on an n-type semiconductor base substrate (a semiconductor substrate) formed by depositing an n−-type semiconductor layer 102 on a front surface of an n+-type supporting substrate 101. The output stage portion is provided with the vertical MOSFET 110 for the output stage. The circuit portion is provided with the horizontal CMOS for the control circuit, and the like. In the circuit portion, only a horizontal n-channel MOSFET 120 is depicted of a horizontal p-channel MOSFET and the horizontal n-channel MOSFET that are complementarily connected to each other to constitute a horizontal CMOS for the control circuit. The protective element portion is provided with a vertical diode 130 to be the protective element portion.
In the output stage portion, the n+-type supporting substrate 101 and the n−-type semiconductor layer 102 respectively function as a drain layer and a drift layer. A drain electrode 109 (a drain terminal) connected to the rear surface of the base substrate (the rear surface of the n+-type supporting substrate 101) is a power source voltage terminal to which an in-vehicle battery is connected (hereinafter, referred to as “VCC terminal”). A ground terminal (hereinafter, referred to as “GND terminal”) and an output terminal (hereinafter, referred to as “OUT terminal”) are provided on the front surface side of the base substrate (the opposite side of the n−-type semiconductor layer 102 from the n+-type supporting substrate 101 side). The OUT terminal is electrically connected to an n+-type source region 107 and a p++-type diffusion region 108 of the vertical MOSFET 110. Reference numerals “103” to “106” respectively denote a trench, a gate insulating film, a gate electrode, and a p-type base region of the vertical MOSFET 110.
The horizontal n-channel MOSFET 120 constituting the horizontal CMOS of the circuit portion is arranged in a p−-type base region 121 selectively provided in the surface layer of the front surface of the base substrate. In an outer periphery of the p−-type base region 121, a p+-type diffusion region 124 is provided to be away from an n+-type source region 122 and an n+-type drain region 123 of the horizontal n-channel MOSFET 120. The depth of the p+-type diffusion region 124 is equal to the depth of the p−-type base region 121 or is deeper than the depth of the p−-type base region 121. FIG. 13 depicts a case where the depth of the p+-type diffusion region 124 is deeper than the depth of the p−-type base region 121. The p+-type diffusion region 124 functions as an inversion preventive layer that prevents inversion of the p−-type base region 121 due to the potential of a wiring layer that is deposited on the front surface of the base substrate.
In the p+-type diffusion region 124, a p++-type contact region 125 is selectively provided to be a contact (an electrical contact portion) with the wiring layer. FIG. 13 depicts an example of a case where the horizontal n-channel MOSFET 120 is used in each of various types of inverter circuits such as a CMOS inverter, an enhanced/depletion (ED) inverter, and a resistance load inverter in the control circuit, and a source electrode connected to the n+-type source region 122 of the horizontal n-channel MOSFET is electrically connected to the GND terminal. The p−-type base region 121 to be a back gate is also electrically connected to the GND terminal through the p+-type diffusion region 124 and the p++-type contact region 125. Reference numeral “126” denotes a gate electrode of the horizontal n-channel MOSFET 120.
The drain terminal connected to the n+-drain region 123 of the horizontal n-channel MOSFET 120 is connected to circuit elements 111 such as the horizontal p-channel MOSFET, a depletion MOSFET, and a resistive element, to constitute the various types of inverter circuits in the control circuit. The circuit elements 111 are connected to an n+-type diffusion region 113 selectively provided in the surface layer of the front surface of the base substrate through a power source circuit 112. The power source circuit 112 includes high voltage circuit elements (not depicted), receives a power source voltage potential (a potential of the VCC terminal) of the n-type semiconductor base substrate, and outputs a low potential to the circuit elements 111 to supply the power source voltage to the various types of inverter circuits that are constituted by the horizontal n-channel MOSFET 120 and the circuit elements 111. A high surge tolerance is required of this in-vehicle power IC.
When high surge voltage such as electro-static discharge (ESD) or the like is applied between the VCC terminal and the GND terminal, a surge sequentially intrudes in the n−-type semiconductor layer 102, the power source circuit 112, the circuit elements 111, the horizontal n-channel MOSFET 120, and the GND terminal along a path from the VCC terminal, and a high voltage is applied. Of the constituent components that the surge intrudes in, the circuit elements 111 and the horizontal n-channel MOSFET 120 each has a small size, and each of the elements as a single component has a low surge tolerance. The vertical diode 130 for absorbing surge current (for protection from surge) is therefore connected in parallel between the VCC terminal and the GND terminal. The vertical diode 130 includes a pn-junction formed by selectively providing a p+-type diffusion region 131 in the surface layer of the front surface of the base substrate. To avoid increases in the number of the process steps in forming the vertical diode 130 in the same n-type semiconductor base substrate as that of the horizontal re-channel MOSFET 120, a p+-type diffusion region 131 of the vertical diode 130 is formed concurrently with the p+-type diffusion region 124 of the horizontal n-channel MOSFET 120.
The vertical diode 130 is subject to avalanche breakdown when surge voltage is applied between the VCC terminal and the GND terminal, and thereby causes a current I101 to flow in the vertical direction from the VCC terminal side toward the GND terminal through the p+-type diffusion region 131 and a p++-type contact region 132 to absorb the surge current. Meanwhile, a pn-junction similar to that of the vertical diode 130 is formed between the p+-type diffusion region 124 and the n−-type semiconductor layer 102 provided in the circuit portion (the region in which the horizontal n-channel MOSFET 120 is provided). The pn-junction between the p+-type diffusion region 124 and the n−-type semiconductor layer 102 also are subject to breakdown by an applied voltage that is substantially equal to that for the vertical diode 130. This is equivalent to plural vertical diodes 127 whose pn-junction areas are each smaller than that of the vertical diode 130 (hereinafter, referred to as “circuit portion diode”) being incorporated in the circuit portion, and a portion of the circuit portion occupying a large area in the power IC being usable as the vertical diode 130 for surge protection. The effective pn-junction area of the vertical diode 130 for surge protection can therefore be increased.
The breakdown current amount (the maximal current value that does not cause current breakdown) of the vertical diode 130 increases in proportion to the pn-junction area. By configuring the circuit portion diode 127 using the portion of the circuit portion, the resistance to breakdown of the vertical diode 130 itself can therefore be improved relative to a case where the vertical diode 130 is configured alone and associated with this, the surge tolerance of the power IC can be improved. The breakdown voltage of the vertical diode 130 is increased with an increase of the temperature. Even assuming that current concentrates at the circuit portion diode 127 that is configured using the portion of the circuit portion and that has a small pn-junction area, the breakdown voltage of the circuit portion diode 127 is therefore increased by heat generation and the concentration of the current at the circuit portion diode 127 is alleviated. Local breakdown of the circuit portion therefore tends to be avoided even when the circuit portion diodes 127 are scattered in the circuit portion as above.
On the other hand, without limitation to the power IC, a technique is generally known of improving surge tolerance using a bipolar element as a protective element for surge protection instead of a diode. When a bipolar element is used as a protective element for surge protection, the surge tolerance of an element to be protected is improved by improving the capacity to absorb surge current using the snapback property of the bipolar element. The snapback property of the bipolar element depends on the device structure, and a protective element including various types of bipolar structures has therefore been proposed to improve this property (see, for examples, Japanese Laid-Open Patent Publication Nos. 2006-93361, 2009-64974, 2011-18685, 2012-38974, 2012-94797, 2012-99626, H3-49257, 2010-287909, 2010-182727, and 2010-157642). In Japanese Laid-Open Patent Publication No. 2006-93361, the base width of a base layer of a bipolar ESD protective element is increased by providing a semiconductor layer of the same semiconductor type as that of and continuous with a lower portion layer of the base layer of the bipolar ESD protective element, to thereby improve the breakdown voltage property of the bipolar ESD protective element itself.
In Japanese Laid-Open Patent Publication No. 2009-64974, a contact portion between a base electrode and a base region of a protective element is positioned between an end on the side of a collector electrode of the base region and an emitter region, and a hold voltage of the protective element is thereby increased. In Japanese Laid-Open Patent Publication No. 2011-18685, the bipolar operation of a protective element is started using a breakdown of a trigger element as a trigger, and the ESD capacity and the noise tolerance are thereby improved. In Japanese Laid-Open Patent Publication No. 2012-38974, a configuration is employed for a thyristor that is a protective element to be operated using a breakdown of a bipolar transistor as a trigger, and the trigger voltage is adjusted independently from the hold voltage of the thyristor. In Japanese Laid-Open Patent Publication No. 2012-94797, a recess is formed in a bottom portion of a body layer under an n+-type source layer of a protective element and the snapback voltage of the protective element is set to be lower than the snapback voltage of an element to be protected.
In Japanese Laid-Open Patent Publication No. 2012-99626, only the trigger voltage is adjusted without varying the hold voltage by adjusting the interval between a second conductivity type layer and a base layer provided inside the low concentration collector layer of a protective element. In Japanese Laid-Open Patent Publication No. H3-49257, increases in the chip area are suppressed by forming on a bottom surface of an impurity diffusion layer or a semiconductor layer formed in each partitioned region, a pn-junction diode whose reverse avalanche voltage is set to be higher than the normal operation voltage of a semiconductor device and to be lower than the breakdown voltages of the elements constituting the semiconductor device. In Japanese Laid-Open Patent Publication No. 2010-287909, the ESD capacity and the surge tolerance are increased by setting the resistance during a breakdown operation of a diode to be smaller than the resistance during a breakdown operation of a transistor and setting a secondary breakdown current of the diode to be larger than a secondary breakdown current of the transistor. Japanese Laid-Open Patent Publication Nos. 2010-182727 and 2010-157642 each discloses a method of suppressing the voltage at which a parasitic bipolar element starts to snap back.